Use High-Performance Clock Buffers to Preserve Clock-Tree Timing Integrity

Circuits, boards, and systems for applications such as wireless base stations, factory automation, data centers, and medical imaging increasingly rely on precise, synchronized clock signals to pace their operations. In many cases, timing clocks must be distributed from one or a few sources to multiple destination subcircuits and functions. This is achieved through a clock distribution topology that includes a clock oscillator, often supported by clock buffers, clock generators, jitter cleaners, and network synchronizers.

While the clock buffer’s primary function is buffering (replicating a signal from a source to isolate it from the influence of the driven load), designers are also looking for differentiation among the various buffer IC options, including expanded clock-signal fanout, level-shifting voltage translation, and input/output compatibility and matching. At the same time, increasingly demanding applications require minimal jitter, skew, and power consumption.

This article explores the seemingly simple function of clock buffers and the challenging requirements designers face when selecting and using these devices. It then introduces example clock buffers from SiTime and shows how they address these challenges.

The role of the clock buffer

The clock network generated and distributed within a digital system is often called a clock tree (Figure 1). It exists in both discrete circuits and entirely within a complex IC. In addition to the clock source, the tree may include clock buffers, jitter cleaners, and network synchronizers along the path to the load. The number of clock tree components and outputs depends on the system’s complexity.

Figure 1: The clock can be distributed directly to multiple clock users (left) or through buffers (right) to maintain clock signal integrity at the various load endpoints. (Image source: Tech Simplified TV/Learn and Design Semiconductors)

The buffer provides drive and isolation, ensuring that endpoint loads see a clock as close as possible to the source clock in terms of timing and waveform integrity. The buffer also prevents variations in load from adversely affecting the primary clock output and other load points in the tree.

Some buffers implement additional functions. These include distributing to multiple loads (fanout), selectively rerouting buffered signals, dividing the signal frequency by an integer value, translating signal-level formats, and translating voltage levels.

Begin with buffer performance parameters

The ideal clock buffer would provide the required separation between the source and the load, along with any additional drive current the load requires. However, no buffer is ideal, so it must be evaluated against various performance considerations. The primary factors used to select the appropriate clock buffer include:

• Maximum operating frequency: This is the highest input clock rate the buffer can accept and reproduce while meeting its specified performance.
• Propagation delay (input to output): This is defined as the time lag from when a clock signal appears at the buffer input to when it is reproduced at the output. If the clock only has one load, this delay may not be critical; in other configurations, it can be an important figure of merit.
• Additive jitter: Introduced by the buffer, it degrades the clock precision as seen by the buffer's load(s). It can cause loss of timing synchronization and other undesired effects.
• Output-to-output skew: This is the time differential between multiple clock outputs from a single buffer. High skew can lead to synchronization issues between subcircuits and loss of timing alignment.
• Input isolation: This measures coupling from an unselected clock input into the active output path. It applies only to buffers that allow selection among multiple clock sources.

Rise and fall times are among the many factors that contribute to propagation delay, jitter, and skew. Slower rise and fall times introduce more uncertainty in the buffer's digital switching action. At the same time, faster rise and fall times can introduce more clock noise and ground bounce, both of which are detrimental to the buffer and overall system performance.

To support diverse application needs and priorities, SiTime offers a wide range of buffers in their high-performance series, supporting frequencies up to 2.1 gigahertz (GHz) and compatibility with multiple standard input types. These buffers feature low propagation delay, jitter, and channel-to-channel skew, among other desirable attributes.

Specifications vary by device, but the family includes buffers with output-to-output skew as low as 30 picoseconds (ps) typical, additive jitter from 50 to 55 femtoseconds (fs) RMS, and propagation delay below 1.6 nanoseconds (ns).

Supporting input and output types and formats

High-speed circuits use a variety of input and output signal types. In some cases, these are needed to maintain compatibility with the rest of the system; in others, they are used to improve signal integrity and noise performance. For these reasons, a clock buffer may also be used for voltage level translation.

SiTime clock buffers support a range of input types: differential low-voltage positive emitter-coupled logic (LVPECL), low-voltage differential signaling (LVDS), low-voltage complementary metal oxide semiconductor (LVCMOS), current-mode logic (CML) (ac-coupled only), high-speed current-steering logic (HCSL), stub series terminated logic (SSTL), and single-ended clocks. This enables the buffers to serve a wide range of clock sources and types.

On the drive side, buffers can interface with LVPECL, LVDS, HCSL, or high-impedance (Hi-Z) modes. These compatibilities allow the buffers to support many clock-tree signal requirements.

To enable this signal translation and level shifting, the buffers in this high-performance series can operate across a range of independent input and output voltages. These include a 3.3 V/2.5 V core supply and independent 3.3 V/2.5 V output supplies, as well as 3.3 V/2.5 V/1.8 V operation for the single-ended LVCMOS output driver.

Implementing a high-speed fanout buffer

A clock buffer for these frequencies is much more than a simple digital IC with direct wiring acting as a repeater. Instead, the buffer operates in the realm of transmission lines, where impedance and reflections are important design considerations.

The SIT92211AI-N (Figure 2) is a good example. This 2.1 GHz, low-jitter, 10-output fanout buffer with multiple user options comes in a 48-pin, 7 mm × 7 mm QFN package.

Figure 2: The SIT92211AI-N clock buffer lets the user select one of three clock inputs and then distributes the selected clock to two banks of five outputs. (Image source: SiTime)

Using this buffer, the system can select a clock input from one of three sources via pin strapping: a primary oscillator, a secondary oscillator, or an 8 to 50 MHz crystal. The primary and secondary inputs support differential formats as well as single-ended clock signals. The selected clock can be distributed to two independent output-drive banks, A and B, and to one LVCMOS output.

On the output side, the output drivers of each bank can be independently programmed for LVPECL, LVDS, HCSL, or Hi-Z modes. The LVCMOS clock output is synchronized to the selected clock and can be enabled or disabled without glitches via a control signal.

There are many possible interface configurations between the clock source and the clock buffer, each requiring careful consideration of implementation details. The datasheet for the SIT92211AI-N identifies 10 configurations and provides an illustration and discussion of each.

For example, a differential input can be wired to accept LVCMOS single-ended levels in AC-coupled mode (Figure 3). This configuration requires that the sum of the driver's output impedance (R_o) and the series resistance (R_s) match the transmission line impedance. The datasheet explains the role of each component in achieving a proper interface and impedance match, which may not be obvious to less-experienced interface designers.

Figure 3: Shown is the AC coupling arrangement for an LVCMOS clock to the SiT92211AI-N. (Image source: SiTime)

The datasheet also shows a circuit for a different interface requirement. In contrast to the AC-coupled interface, a differential input can be wired to accept LVCMOS single-ended clock signals in DC-coupled mode (Figure 4).

Figure 4: Shown is a configuration for DC coupling an LVCMOS clock to the SiT92211AI-N. (Image source: SiTime)

As in the previous example, this configuration also requires that the sum of R_o and R_s equal the transmission line impedance.

Clock buffering for automotive systems

Today’s automobiles are highly computerized systems. For this reason, they also need clock trees for their processors and for establishing network timing. The problem is the harsh environment, which requires components that meet relevant automotive standards; for ICs, the standard is AEC-Q100, in one of several temperature grades.

To meet AEC-Q100, SiTime offers the SIT92184AA-N clock buffer IC (Figure 5), a 200 MHz device with a basic 1:4 fanout. This Automotive Grade 1 (-40°C to +125°C) high-performance LVCMOS clock buffer has an additive phase jitter of just 50 fs RMS and a very low pin-to-pin skew of less than 50 ps. Offered in an 8-pin 2 mm × 2 mm DFN package, it can operate from a 1.8 V to 3.3 V supply.

Figure 5: The automotive-qualified SIT92184AA-N clock buffer IC provides a basic 1:4 fanout. (Image source: SiTime)

A special feature of the SIT92184AA-N is its synchronous, glitch-free output-enable (OE) function, which prevents incomplete or malformed clock pulses when the outputs are enabled or disabled. The device also has a nominal 50 Ω output impedance, simplifying series termination when driving 50 Ω transmission lines. On the input side, the source driver and any external series resistor must be selected so that their combined impedance matches the transmission line (Figure 6).

Figure 6: Shown is the recommended input-clock connection for the SIT92184AA-N; the source driver’s R_o and the external R_s combine to match the 50 Ω transmission line. (Image source: SiTime)

Conclusion

The system clock function is conceptually straightforward, but ensuring that a high-speed clock reaches all loads with intact timing and original integrity is both a strict requirement and a challenge. Clock buffer ICs provide clock-signal drive and fanout (if needed) to maintain clock-signal fidelity from the source to all loads. SiTime offers a range of clock buffers with the required performance for high-speed, low-jitter, low-skew, and minimal delay, ensuring reliable, consistent performance at the overall system level.