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Learn how to implement a bid/ask order book on an FPGA using SystemVerilog arrays to maintain best-bid and best-ask values.
Build a “Big Brother eye” that awakens in darkness using LDR sensing and Arduino code driving a GC9A01 LCD.
Create a DIY simple oscilloscope using Arduino Mega, an LCD, and push buttons to measure voltage, frequency, and more.
In this post, we size and simulate a common-source amplifier circuit in the Cadence Virtuoso tool using the gm/Id methodology and the open-source SKY130 PDK.
Previously, we looked at the peripheral side implementation of the Serial Peripheral Interface (SPI) protocol in SystemVerilog. Now, let’s take a closer look at designing the controller in SystemVerilog.
Learn how to build a circular FIFO in SystemVerilog with read/write control and pointer logic.
Explore how inverter sizing affects propagation delay and oscillation frequency in a ring oscillator.
Learn how to design and simulate an ITCH protocol parser in SystemVerilog for FPGAs. Explore the intersection of FPGA design and finance.
Learn how to design and simulate a SPI peripheral module in SystemVerilog using Quartus and Modelsim.
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