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Sizing of a Common Source Amplifier Circuit Using gm/Id Methodology
In this post, we size and simulate a common-source amplifier circuit in the Cadence Virtuoso tool using the gm/Id methodology and the open-source SKY130 PDK. Traditionally, MOSFET device saturation currents have been defined by the golden square law equations:
1) NMOS: The current equation in the saturation region (VDS > VGS − Vth) is given by
Id = 1/2 μnCoxW/L(VGS − Vth)2(1 + λVDS) (1)
2) PMOS: The current equation in the saturation region (VSD > VSG − Vth) is given by
Id = 1/2 μnCoxW/L(VSG − Vth)2(1 + λVSD) (2)
To build amplifiers, we bias them in the saturation region. However, as device size shrinks, the behavior of MOSFETs in the saturation region has been deviating from the square law equation, so hand calculations are no longer effective in designing circuits. As such, we have to transition to the gm/Id methodology to size transistors with fewer iterations.
The deviation between the golden square law and actual transistor behavior is shown in Figures 1 and 2.
FIGURE 1: Real device vs square law
FIGURE 2: gm/Id vs square law
Lookup table
Depending on the overdrive voltage of the biased transistor, we have weak, medium, and strong inversion of the channel. We can generate lookup tables for a transistor to see how the gm/Id ratio (inversion level) affects the transistor's intrinsic gain, transit frequency, and current density. The gm/Id ratio is a measure of transistor efficiency - how much current we can get given gm.
For the open-source SKY130 PDK we use in our amplifier design, we can find an interactive web-based lookup table at http://www.open-lut.org. The minimum channel length we can use in our design is 150nm to avoid manufacturing errors dropping the fabrication to below 130nm.
The lookup table from the web is shown in Figure 3.
FIGURE 3: Open-LUT: Open-Source PDK Lookup Tables
Common Source amplifier schematic in Cadence
FIGURE 4: Schematic of a common-source amplifier
Circuit analysis:
The figure consists of an NMOS common-source amplifier with a PMOS active load, and the current is set through a current mirror and an ideal current source. We have a capacitive load at the output, which behaves as an open at DC gain.
The DC gain (Av(0)) is given by
Av(0) = gm(ro,n||ro,p) = gm*Rout = gm/(gds,n+gds,p)
The bandwidth is given by
BW = Av(0) * fcut-off = [gmRout] [1/(2π*Rout*CL)]
= gm/(2π*CL)
Design goals and parameter selection:
Design constraints:
Let us set the design specifications of 25dB DC gain and 60MHz unity gain bandwidth. The load capacitance is set to 2pF.
To prevent second-order effects and approximation errors, we will try to design for 18 V/V (27dB = 17.7 V/V rounded up) of gain and 66MHz of bandwidth.
Additionally, we will aim to set the output node midway at 0.9V DC.
From equation (4), we calculate gm = 66MHz * 2π * 2pF = 0.82938mS.
If we take equation (5) and design for gds,n = gds,p, then we get gds = 1.106mS / (2×22.4) = 23.038uS.
This gives us a gm/gds ratio of 36.
To avoid weak inversion of the channel, we will target Vov > 150mV. For this, we can choose a gm/Id value of 7 (strong inversion).
Lookup table
Given our constraints, we can input values at http://www.open-lut.org. Inserting VDS, gm, gds, and gm/gds and gm/Id populates the entire table.
FIGURE 5: NMOS parameters
For the PMOS, we set the Id to be what we found for the NMOS, which is 118.5μA. We know gds of the NMOS and PMOS are the same. Finally, we choose a gm/Id value of 7.
This gives us all the values we need. Note that we do not need to use the VGS value given by the table since we have an ideal current source and a 1:1 current mirror.
FIGURE 6: PMOS parameters
Bode plots
Close, but does not meet specifications.
FIGURE 7: Bode plot showing target gain not met
After we simulate the design, we see that the unity gain bandwidth is met, but the gain falls just short of 25dB. We used a smaller excess margin for the gain compared to the unity-gain bandwidth, but this shows how powerful the gm/Id methodology is.
Fix: Up size channel length
In order to remedy this situation, we can increase the length of the NMOS while scaling the PMOS at the same ratio. By keeping the W/L ratio constant, we keep the same current flowing through the transistors. Additionally, a larger L means more resistance and higher gain. It also means the pole gets closer since the gate capacitance increases, but the simulated AC analysis shows that we have some leeway. Hence, I change the W/L ratio to 4um/265nm. This choice satisfies our targets.
FIGURE 8: Bode plots showing specs met
Conclusion
Golden Square Law behavior of MOSFETs in saturation is a good starting point to analyze circuits, but in order to design circuits, it falls short. The channel length modulation changes based on the current and length of the transistor. In weak and moderate inversions, gm/Id is not equal to 2/Vov anymore. As such, analog IC designers can use the gm/Id method to get insight into actual transistor behavior and meet their targets with fewer iterations compared to being a 'SPICE monkey.'
